The SrcFFOverflow_n and SnkFFOverflow_n signals are indicating "full" instead of "overflow." When these signals are asserted, the FIFO is full but that does not necessarily mean that it has overflowed. Consequently, data might not have been dropped when the signals are asserted.
To ensure that data is not lost, check for missing data segments in your simulation or in the received packets. Unless there is a way to detect all missing data, it is safe to assume that the FIFO has overflowed. Xilinx recommends that you reset the FIFO by asserting SnkFifoReset_n or SrcFifoReset_n when SnkFFOverflow_n and SnkFFOverflow_n are asserted.
Typically, if you have incorporated some form of flow control using SnkAlmostFull_n or SrcFFAlmostFull_n, overflowing the FIFO is unlikely.
This issue will be fixed in v6.3.