When implementing a non-guided PCI LogiCORE design in a Virtex-II Pro device, it is possible that PAR will report timing violations in the timing summary portion of the PAR report. It appears that all constraints have been met. Why is this occurring?
The setup/hold summary of the timing report is showing positive hold times on some PCI pins. Why is this occurring?
This should happen only on non-guided Virtex 2 Pro designs. If you see this occur on a 66 MHz PCI Core design using a guide file, make sure you are using version 3.0.145 of the PCI Core or higher. Also, make sure you are using version 7.1i or higher of the ISE design tools.
If this is a 66 MHz PCI Core design in a Virtex-II Pro or Virtex 4 device, ensure the input delay buffer settings are correctly set. For information on the settings for the Virtex-II Pro device, refer to Table 3-3 on page 27 of the Getting Started Guide under the "Family Specific Considerations" section. The Getting Started Guide can be found in the docs directory of the PCI Core download.
If the problem persists, open a WebCase and refer to this Answer Record number at:
If this is a 33 MHz PCI design which does not use a guide file, this behavior is due to hold time violations. Run TRCE and look for hold time violations. The hold times on all PCI pins should be 0 or less. At the end of the TRCE report, you will find a table titled, "Setup/Hold to clock PCLK." Here you will find that some pins such as TRDY_N have small positive hold times.
This will be fixed in the next major ISE software release.
Until then, this can be corrected by re-running the router and not running the placer on the design. First place-and-route the design as normal, and if hold violations exist run PAR again using the following command line options:
par -w -p -k pcim_top_routed.ncd output pcim_top.pcf
Please refer to the Development System Reference Guide in the 6.1i Software Manuals for more information on PAR options.