AR #19385 - OPB/PLB DDR - How do I determine EDK DDR controller timing?
OPB/PLB DDR - How do I determine EDK DDR controller timing?
| AR# | 19385 |
| Part | IP-Processor |
| Last Modified | 2004-07-15 00:00:00.0 |
| Status | Active |
| Keywords | DDR, OPB, PLB, timing, trace, DCM, phase, shift, controller, SDRAM, board |
Description
Keywords: DDR, OPB, PLB, timing, trace, DCM, phase, shift, controller, SDRAM, board
Urgency: Standard
General Description:
How do I perform a board-level timing analysis on a design utilizing an EDK DDR controller?
Solution
See the following PDF file for an example analysis:(Xilinx File ftp://ftp.xilinx.com/pub/applications/misc/ar19385.pdf)