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AR# 19385

OPB/PLB DDR - How do I determine EDK DDR controller timing?

Description

General Description:

How do I perform a board-level timing analysis on a design utilizing an EDK DDR controller?

Solution

See the following PDF file for an example analysis:

(Xilinx File http://www.xilinx.com/txpatches/pub/applications/misc/ar19385.pdf)

AR# 19385
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article