We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19389

6.2i ISE/EDK - Poor integration of embedded proc into ProjNav using Verilog flow results in "Could not find module/primitive 'myproc'"


Keywords: ISE, Project Navigator, XST, embedded, processor, module, primitive, Verilog

Urgency: Standard

General Description:
Adding an embedded processor (myproc) into an ISE project (using Project -> New Source -> Embedded Processor) results in the following error when synthesizing the top level file instantiating the processor system:

"ERROR:HDLCompilers:87 - top.v line 6 Could not find module/primitive 'myproc'
ERROR: XST failed
Process "Synthesize" did not complete."


This error occurs only when the top level file is Verilog. In the VHDL flow, the myproc is seen as a black box and XST fetches the "myproc.ngc" and other netlist files. However, for the Verilog flow, XST fails to look for "myproc.ngc" file. Adding a synthesis attribute for the processor system does not fix the issue.

This problem has been fixed in the latest 6.3i Service Pack available at:
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19389
Date Created 05/02/2004
Last Updated 03/20/2006
Status Archive
Type General Article