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AR# 19404

LogiCORE Gigabit Ethernet MAC v4.0 - Simulating with the demo testbench leads to X_FF Hold violations and Xs on outputs

Description

General Description: 

When I am simulating the Gigabit Ethernet MAC v4.0 Core with the PHY interface using the demo testbench in 6.2i (or newer), the following warnings occur in ModelSim, which leads to Xs on outputs of the core: 

 

VHDL: 

 # ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; 

 # Expected := 0.34 ns; Observed := 0.284 ns; At : 33790.344 ns 

 # Time: 33790344 ps Iteration: 3 Instance: /testbench/dut/gmac_core_bu2_u0_flow_tx_data_int_1 

 

Verilog: 

 # ** Error: C:/Xilinx_62/verilog/src/simprims/X_FF.v(39): $hold( posedge CLK:33780060 ps, posedge I &&& (in_clk_enable == 1):33780344 ps, 340 ps ); 

 # Time: 33780344 ps Iteration: 0 Instance: /testbench/DUT/\gmac_core/BU2/U0/FLOW_TX_DATA_INT_1\

Solution

This is a simulation only issue with the demo testbench. Specifically, the problem is related to setup and hold timing of the IOs that connect the client side signals to IOBs for demonstration purposes. When the GMAC Core is integrated into your actual design, the client side signals will be connected to internal logic and these timing issues will not exist. 

 

To resolve this issue with the Gigabit Ethernet MAC v4.0 demo testbench, install the patch that is available in the LogiCORE Gigabit Ethernet MAC v4.0 Release Notes (Xilinx Answer 18571). The patch includes a demo testbench with the timing on the client side IOs adjusted for 6.2i.

AR# 19404
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article