We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19448

7.1i XST - How do I use the `ifdef to skip embedded meta-comments in the Verilog code?


Keywords: XST, ifdef, synthesis, directive, preprocess

XST processes all synthesis directives, regardless of whether they are enclosed within an `ifdef `endif pair, as in the following example:

`ifdef my_define

// synthesis attribute iostandard of my_port is LVCMOS33;


How can I embed meta-comments in the `ifdef `endif pair?


Currently, it is not possible to embed meta-comments inside of `ifdef `endif constructs. One possible way to work around this issue is to use the new Verilog 2001 attribute passing as follows:

`ifdef my_define

(* iostandard = "LVCMOS33" *)
input my_port;


Refer to the XST User Guide for more information on Verilog 2001 attribute passing:
AR# 19448
Date Created 09/03/2007
Last Updated 01/07/2009
Status Archive
Type General Article