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AR# 19477

7.1i CoolRunner XPLA3 CPLDFit - "WARNING:Cpld:1081 - Cannot assign signal 'Data<0>' to location 'B15=FB1_2'. Not enough Control Terms."

Description

General Description:  

When fitting my CoolRunner design, a message similar to the following precedes a Fitting error message: 

 

"WARNING:Cpld:1081 - Cannot assign signal 'Data<0>' to location 'B15=FB1_2'. Not enough Control Terms."

Solution

The CoolRunner XPLA3 function block includes flexible control terms (CT) to use as local clocks, clock enables, asynchronous preset/resets, and output enables. There are eight control terms available in each function block. In the CoolRunner data sheet, the "XPLA3 Macrocell Architecture" figure in the "Macrocell Architecture" section shows the distribution of control terms within a function block. You can access this data sheet at: 

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-18742&iLanguageID=1
 

If four equations in the same function block use the same asynchronous reset, then only one CT is required and it is shared with the four equations. If these four equations have four unique asynchronous resets, then four CTs are required. If these four equations also have unique asynchronous presets, then four additional CTs are required. However, the figure in the data sheet shows that of the eight CTs in a function block, only six are available for asynchronous reset and preset; this illustrates why a design might not fit.  

 

In CPLDs, pins are directly connected to the macrocell that drives it. Consequently, if a design has pin-locks, it is also locking registers to macrocells (and their associated function blocks).  

 

If a design has five registers locked to the same function block, then it must have enough control term resources to meet the needs of this logic for a successful fit. The warning message is an indication that there are not enough CT resources within the function block to meet the pin-locking requirement.  

 

The following are different ways to work around this issue: 

- Adjust the pin-out so that registered output equations are spaced into separate function blocks. 

- Adjust the design to remove unnecessary unique control term usage (for example, use synchronous reset or preset as opposed to asynchronous reset or preset, and use synchronous load as opposed to asynchronous load). 

- Add buffer logic so that the pin-out can be maintained, and the register becomes a node that can be placed anywhere in the device. For examples on creating buffer logic, see (Xilinx Answer 7595).

AR# 19477
Date Created 09/03/2007
Last Updated 05/08/2014
Status Archive
Type General Article