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AR# 19481

6.2 EDK - How do I instantiate the ILA core with ChipScope Pro Generator in my EDK design?


General Description:

In XPS 6.2, I cannot find the ChipScope ILA core. How do I instantiate the ILA core to probe signals?


The "chipscope_ILA" component will be available in EDK 6.3.

In the meantime, you can use the following flow to instantiate the ILA core in an EDK design. To use this flow, you must have EDK 6.2 and ChipScope Pro 6.2i with the latest Service Packs for both. Xilinx recommends this flow if you are using the MDM debugger, or if you already have a ChipScope core (such as IBA or VIO).

1. Open ChipScope Generator.

2. Select the ILA (Integrated Logic Analyzer).

3. Select a folder for the output netlist.

4. Use the online ChipScope Pro 6.2i User Manual to configure the ILA, accessible at:

Make sure that you enable the Trigger Output Port for the Trigger Output Settings.

5. Once you have generated the netlist, exit ChipScope Generator.

6. XPS needs an HDL wrapper for each IP. You can make one for the ILA using the ila_xst_example.vhd (or .v) template generated by ChipScope Generator. This file contains the ILA port list. Use "chipscope_ila" for the name of the entity.

7. Open XPS.

8. Use the Import Peripheral Wizard to add the ILA to your XPS project (Tools -> Import Peripheral Wizard). Ensure that the name of the IP matches the entity of your wrapper (should be "chipscope_ila"). There are no bus interfaces for this IP. Then select the HDL wrapper and the "ila.edn" (netlist). Click "More Info" if you need help to import a peripheral.

9. This IP will now be on the component list, and you can add it to your PBD schematic. By double-clicking it (object properties), add all the ports (clk, control, trig0 and data, depending on if the data are the same as the trigger, or not). Do not add trig_out.

10. You now need to add the "chipscope_icon" to your design. If you already have one (for instance, if you are using the "chipscope_vio" or "chipscope_iba"), modify the parameter C_NUM_CONTROL_PORTS (object properties of the "chipscope_icon") to add one more port. If you do not already have one, add it to your design, and select '1' for this parameter. For more information, see the PDF documentation for the "chipscope_icon" component.

11. The second parameter of the "chipscope_icon", named C_SYSTEM_CONTAINS_MDM, must be set to '1' if you are using the MDM debugger. If set to this value, ChipScope will use the BSCAN component instantiated by the MDM. If set to '0', the "chipscope_icon" will instantiate a BSCAN component.

12. Open the MHS file to make the following connections :

a) Control(IN) of the "chipscope_ila" must be connected to control(OUT) of the "chipscope_icon".

b) Clk(IN) of the "chipscope_ila" is the Trigger clock. Xilinx recommends connecting this clock to the system clock.

c) Trig0(IN) of the "chipscope_ila" is the Trigger signal(s). If you have selected "Data same as trigger" in ChipScope Generator, then it is also your data. If you want to connect multiple signals to this trigger bus, use the "&" to concatenate them (for instance : PORT trig0=SDRAM_8Mx32_SDRAM_WEn&SDRAM_8Mx32_SDRAM_CKE if trig0 is 2 bits width). You can also have multiple ports (trig1, trig2,etc...) depending of the number that you have selected in ChipScope Generator.

d) Data(IN) of the "chipscope_ila" is the data signal. Follow Step c) to connect the data. If you have selected "Data same as trigger" in Chipscope Generator, this port does not exist.

13. Save the project, go to "Tools" and select "Generate Bitstream".

14. Run the FPGA Editor and open the system.ncd file in <project_directory>/implementation.

15. Go to "Tools" and "ILA" to make sure that the ILA is correctly implemented in your design. If a message appears stating "There is no ILA core", check the component list for instances starting with U_icon_pro or U_ila_pro. If you have these instances, the ILA is correctly implemented.

16. Finally, you can run ChipScope Pro Analyzer 6.2i (follow the ChipScope User Manual for this tool) to program the FPGA using the system.bit file in "project_directory>/implementation", and start debugging your design.

NOTE: One limitation is that you cannot probe internal signals with this flow. You can probe only signals that are in the MHS file (such as ports of the IPs in your design), unlike the flow with ChipScope Inserter. See (Xilinx Answer 19423).
AR# 19481
Date Created 09/03/2007
Last Updated 08/17/2011
Status Archive
Type General Article