UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19499

6.2 System Generator for DSP - Why is there a PicoBlaze simulation mismatch during the first clock cycle when the first instruction is arithmetic or logical?

Description

General Description: 

Why is there a PicoBlaze simulation mismatch during the first clock cycle when the first instruction is arithmetic or logical?

Solution

This is a known issue in System Generator for DSP 6.2 and will be fixed in System Generator for DSP 6.3. 

 

The mismatch occurs only for the first clock cycle (first time step) if the instruction is arithmetic or logical. 

 

The simulation starts as if there were a register, but since there is not a register, when you perform the VHDL simulation, a mismatch occurs for the first clock cycle.

AR# 19499
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article