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AR# 195

FPGA Configuration (4000E/XL/XLA) - Which pins are driven during clear/initialization? (master parallel)


General Description:

Which configuration pins are actively driven during the power-up, clear, and initialization stages of configuration for the XC4000E/XL/XLA family?


When configuring an FPGA device in master parallel mode, the address lines remain 3-stated after power-up until after the INIT has gone high and the Mode pins have been sampled. This occurs after the clear and initialization stages in the configuration process.

Note that all configuration mode specific pins (such as CCLK, RDY/BUSY, etc.) are 3-stated during the clear and initialization stages. However, the HDC, LDC, Done, Init, and Dout pins will begin driving as soon as the chip reaches the threshold voltage.

AR# 195
Date Created 08/21/2007
Last Updated 05/08/2014
Status Archive
Type General Article