UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19500

6.2 System Generator for DSP - Why is one of my clock (CLK)/clock enable (CE) ports missing when I import my HDL as a black box into System Generator for DSP?

Description

Why is one of my clock (CLK)/clock enable (CE) ports missing when I import my HDL as a black box into System Generator for DSP?

Solution

If the two clocks or clock enables are set to the same rates, the block_interface_wrapper file created for HDL CoSim omits one of the clock/clock enable pairs.

It the clock and clock enable ports are to be run at the same rate, you can work around this issue by connecting the 2 clocks and the 2 clock enables together in the HDL, creating a single clock/clock enable pair.

This issue is resolved in System Generator for DSP 6.3.

AR# 19500
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article