UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19505

8.2 System Generator for DSP - Why are there back annotation simulation mismatches when simulating a reloadable DA FIR?

Description

Why are there back annotation simulation mismatches when simulating a reloadable DA FIR?

Solution

The problem is that there are errors on the RFD initially, which cause a mismatch on the valid out and data outputs of the same block. The errors are seen in short little bursts, then the simulation gets back on track again.

AR# 19505
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article