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AR# 19515

Virtex-II Pro - Speeds Files Revision History

Description

This Answer Record contains the speeds files revision history for the Virtex-II Pro FPGA family.

Solution


Speeds Files Revision History



1.93 Release: Description and Explanation of Changes

- Added support for xq2vp40 and xq2vp70



1.92 Release: Description and Explanation of Changes

- All supported devices are now PRODUCTION

- Updated frequency values for MGT components



1.91 Release: Description and Explanation of Changes

- Maximum frequency for the DCM in low-frequency mode is updated to 270 MHz for the -7 speed grade.

- New I/O Standards support is added.



1.90 Release: Description and Explanation of Changes

- GTL* output adjustments are adjusted to be more in line with measured values.

- Added support for SSTLII{_DCI} I/O adjustment.



1.89 Release: Description and Explanation of Changes

- Corrected GT values for the -7 and -6 speed grades.

- Added new I/O adjustments for HSLVDCI_{15, 18, 25, 33}.



1.88 Release: Description and Explanation of Changes

- Updated values for PPC405 and GTIO.



1.87 Release: Description and Explanation of Changes

- Adjusted PCI values.



1.86 Release: Description and Explanation of Changes

- Added support for HSLVDCI_18.

- Adjusted values for LVCMOS_F24 output.



1.85 Release: Description and Explanation of Changes

- Source-synchronous and system-synchronous hold times are smaller.



This change reduces the setup/hold window and allows support for higher-speed designs. The Tiopid parameter has been increased for certain device/speed grade combinations to better match measurement results from characterization. This parameter might affect setup and hold values for designs that use the delay line in the IOB.



- RocketIO TXDATA Setup and Hold Times



This change fixes a bug introduced in 6.1isp3 in which the TXDATA setup and hold requirements were reversed, resulting in the reporting of non-existent hold violations in some designs.



The first version of the design tools containing these fixes is ISE 6.2i.



- TLVCMOS25_F24 was changed because it was yielding a negative number in certain extreme circumstances.



- The GT10 values were being under-reported:

-- Clock delays changed from 1.1 to 1.5

-- Hold delays changed from 0.7 to 1.0

This does not impact the GT10 frequency.



- Values for HSLVDCI_18:

-- Input: 0.733 0.842 0.927

-- Output: 0.808 0.929 1.021



1.83 Release: Description and Explanation of Changes

Minor changes are made to the speeds files, but the values remained the same.



1.81 Release: Description and Explanation of Changes

What did not change in Virtex-II Pro Speeds Files version 1.81?



- The production speeds files for the -5 speed grade for the 2VP7 device remain unchanged.

- The production speeds files for the -5 speed grade for the 2VP20 device remain unchanged.



The following devices and speed grades are designated as production:



- 2VP30, 2VP40, 2VP50, and 2VP70 devices are now PRODUCTION for speed grade -5.

- 2VP7, 2VP20, 2VP30, 2VP40, 2VP50, and 2VP70 devices are now PRODUCTION for speed grade -6.



The remainder of the speed grade designators remain unchanged from the previous (version 1.78) release. Compared to version 1.78 of the speeds files, the following resources are slower:



- An error occurs in a model used in the Horizontal Longs just above and below the PPC (RC_PPC_HLONG). In these two rows, the correct value shows the HLL as slightly slower (250-420ps).



The following resources are now faster:

- Global clock

- Vertical long lines

- Tsrck and Tceck are faster in the -7 and -6 speed grades.



Additional Adjustments:

The input delay line values were placeholders and have been adjusted so that they line up with the silicon.



This model for measuring IOB output delays does not consider the effects of external board-loading on the Xilinx device clock-to-out times. For this reason, it is necessary to perform an IBIS model simulation to generate accurate clock-to-out times.



For more information on performing IBIS simulation, see (Xilinx Answer 17720).



For information on current speeds files versions with respect to design tool releases, see (Xilinx Answer 12201).
AR# 19515
Date Created 09/03/2007
Last Updated 08/19/2010
Status Archive
Type General Article