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AR# 19519

6.2i COREGen - Core generation fails with "WARNING: Cannot generate the <Core_type> core, <Core_Name>, because the license file <name_ver.lic> could not be found"

Description

Keywords: Structure of Behavior, SoB, License, generate, found, SimGenerator, Elaboration, Interleaver, De-interleaver, sid, lic, turboenc, 3GPP2 Turbo Encoder, Reed-Solomon_Encoder

Urgency: Standard

General Description:
For licensed cores, if a license location has not been specified or a license for the core is not found, the core will only be available for simulation. If a user selects the licensed core, a warning is given indicating that the Core is Simulation Only. However, for a small subset of these cores (listed below) generating the simulation data also fails and an Elaboration Error Window pops up, which specifies:
"Not all Output products were generated successfully. View Output Messages?"

Below are two examples of what the Message view says:
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Preparing to elaborate core...
WARNING: Implementation Netlist output will not be generated for core <sid> since no valid license was found.
Generating the .VEO/.V simulation support files...
WARNING: Cannot generate the Interleaver/De-interleaver core, sid, because the license file <sid_v4_0.lic> could not be found.
WARNING: SimGenerator: Failure of Sim to implement customization parameters core sid
WARNING: Did not generate Verilog instantiation template (.VEO) and simulation wrapper (.V) files for core <sid>.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Preparing to elaborate core...
WARNING: Implementation Netlist output will not be generated for core <turboenc_vhd> since no valid license was found.
Generating the .VHO/.VHD simulation support files...
Elaborating the module...
WARNING: Cannot generate the 3GPP2 Turbo Encoder core, turboenc_vhd, because the license file <tcc_encoder_v1_0.lic> could not be found.
WARNING: SimGenerator: Failure of Sim to implement customization parameters core turboenc_vhd
WARNING: Did not generate VHDL instantiation template (.VHO) and simulation wrapper (.VHD) files for core <turboenc_vhd>.
ERROR: Errors encountered while generating turboenc_vhd (3GPP2 Turbo Encoder 1.0). No output files have been generated.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

The cores that exhibit this problem are:

3GPP2_Turbo_Encoder 1.0
Reed-Solomon_Encoder 5.0
Interleaver/De-interleaver 3.1
Interleaver/De-interleaver 3.0
Interleaver/De-interleaver 4.0

Solution

The cores listed above have either their VHDL or Verilog models (or both) generated using Structure of Behavior (SoB).
SOB requires the core to be implemented in order to generate the behavioral model. Because there is no license to generate the core netlist, the instantiation wrapper needed for simulation cannot be created.

To work around this issue, you can obtain an evaluation license to test and simulate any of the licensed cores.
AR# 19519
Date Created 06/04/2004
Last Updated 03/20/2006
Status Archive
Type General Article