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AR# 19547

Spartan-3/-3E FPGAs - What are the AC/DC specifications for overshoot/undershoot amplitudes?


What are the maximum amplitude AC/DC specifications of overshoot and undershoot for Spartan-3/-3E devices?


It is a common design practice to avoid turning on the internal protection diodes to prevent power regulation problems caused by uncontrolled reverse current and stress to the FPGA. To avoid turning on the internal diodes, you must ensure that the input signal meets Vin max/min ratings.

Maximum Overshoot amplitude: Vinmax = Vcco + 0.5V (Vin is not to exceed 4.05 V.)

Maximum Undershoot amplitude : Vinmin = -0.5V (Vcco < 3.3V)

NOTE: Vinmin = Vccomax - Vinx; where Vinx = 4.05V. Consequently, if Vccomax is 3.75V, as specified in the data sheet, Vinmin is only -0.3V. If VCCO is 3.0V, then Vinmax = 4.05V - 3.0V = -1.05V. However, the internal clamp diodes offer protection only against transient voltages up to VCCO + 0.5V and GND - 0.5V. Consequently, when VCCO is 3.0V, the absolute maximum undershoot is -1.05V to avoid stress to the FPGA. However, any undershoot beyond -0.5V requires you to limit the reverse current to 10 mA.

Going beyond the maximum ratings requires that you add external components to protect the FPGA or regulator against reverse current. If you exceed Vinmax, the internal power clamp diode to VCCO turns on and a reverse current is driven into the VCCO rail. If you exceed Vinmin, the internal clamp diode to ground turns on and a reverse current is driven into ground. You must limit the reverse current to 10 mA by using a series resistor, and a shunt resistor might need to be used to divert the reverse current away from the regulator to maintain proper power regulation. For more information on calculating the value of a shunt resistor, see (Xilinx Answer 20496).

AC specifications for overshoot and undershoot are the same as the DC specifications. No duration is specified for how long you can exceed Vin max/min specifications.

For more information about overshoot and undershoot, see (Xilinx XAPP659): "Using 3.3V I/Os in a Virtex-II Pro Design," which also applies to Spartan-3/-3E devices.

For more information on how to calculate the value of a current limiting series resistor, see (Xilinx Answer 19146), (Xilinx Answer 20492).

For additional information on Handling Large Swing Signals on Spartan devices, please see XAPP459: http://www.xilinx.com/support/documentation/application_notes/xapp459.pdf

For additional information on Spartan-3 FPGA 3.3V Configuration, please see XAPP453:http://www.xilinx.com/support/documentation/application_notes/xapp453.pdf

Other relevant references include the Spartan-3 Generation FPGA User Guide (UG331):http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

and the Spartan-3 Generation FPGA Configuration User Guide (UG332):

AR# 19547
Date Created 09/03/2007
Last Updated 02/24/2013
Status Active
Type General Article
  • Spartan-3
  • Spartan-3E