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AR# 19555

12.1 Release Note - Timing - Does Timing Analyzer provide phase shift information on external clocks generated by DCM?


In my design that contains a DCM with external feedback and a fixed phase shift applied (Clk0 drives an OBUF and nothing else), I cannot find any information in the Timing Analyzer timing report indicating that the phase shift applied to the DCM is implemented. How can I find out if my requirement is implemented?


The phase shift applied by a DCM on a clock appears in the timing report on the PERIOD constraint associated with that clock. Since the clock generated by the DCM is going off chip and is not connected to any internal synchronous element, a PERIOD constraint is not reported in the timing report. Consequently, information on the phase shift of the output clock is not displayed.

To ensure that your phase shift requirement is applied and implemented correctly, open your placed and routed design in the FPGA Editor. Select the applicable DCM and click on INFO. The DCM configuration settings are displayed in the FPGA Editor console window, where you can see the actual phase shift implemented by the DCM.

If this DCM did drive internal elements, it is recommended that you use the FEEDBACK constraint to inform the timing analysis of the external board delay of the feedback signal.

AR# 19555
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article