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AR# 19568

Virtex-II Pro RocketIO - Fibre Channel Arbitrated Loop (FC_AL) compliance


Fibre Channel Arbitrated Loop defines multiple primitive signals as fill words for clock correction.  


ARB(x) K28.5, D20.4, VAL, VAL // Arbitrate for Loop, where VAL is the AL_PA address 

IDLE K28.5, D21.4, D21.5, D21.5 // Indicates no operation on the data 


An FC_AL port can insert ARB(x) instead of IDLEs as fill-words between FC data frames. Consequently, to support Fibre Channel Arbitrated Loop, clock correction on both IDLE and ARB(x) is required. However, this exceeds the number of clock correction sequences supported by the Virtex-II Pro MGTs.


To resolve this issue, you can bypass the clock correction in the Virtex-II Pro MGT and implement the clock correction logic in the Virtex-II Pro FPGA fabric. 


Guidelines on Clock Correction in the Fabric 


Clock Correction Sequences 

- For clock correction on ARB(x), a comparison is needed only on the first two bytes, since the third and fourth bytes are the port address. 

- For clock correction on IDLE, a comparison is needed on all four bytes; this is needed as K28.5, D21.4 is not unique to IDLE. 


Bypassing Clock Correction in the MGT 

To bypass clock correction, set MGT attribute RX_BUFFER_USE to FALSE. 


RX Buffer in the Fabric 

You can implement the RX buffer in the FPGA fabric using Distributed RAM or Block RAM per your design requirements. 


Clock Correction Algorithm 

Implement the clock correction algorithm per the Fibre Channel Arbitrated Loop specification.

AR# 19568
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article