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AR# 19577

6.2 EDK Install - Service Pack 2 Release Notes/README

Description

Keywords: UNIX, PC, Linux, software, update, SP1, 6.2i

Urgency: Standard

General Description:
This README Answer Record contains the Release Notes for EDK 6.2 Service Pack 2. The Release Notes include installation instructions and a list of the issues that are fixed by this Service Pack for the 6.2 release.

Solution

1

EDK 6.2i SP2 requires a valid ISE 6.2i or greater installation.

A successful installation of Xilinx EDK 6.2 Service Pack 2 updates your software version number to 6.2.2.

NOTE 1: The destination directory specified during the set-up operation must contain an existing Xilinx EDK 6.2 installation. Only existing files will be updated.

NOTE 2: Set the Xilinx EDK 6.2 environment variable before commencing the installation of Service Pack 1.

Download installation instructions for PC users:

1. Download EDK_6_2_2_win.exe from:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

2. Run "EDK_6_2_2_win.exe".

Download installation instructions for Solaris users:

1. Download EDK_6_2_2_sol.zip from:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

2. Unzip EDK_6_2_2_sol.zip it into your $XILINX_EDK area.

Download installation instructions for Linux users:

1. Download EDK_6_2_2_lin.zip from:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

2. Unzip EDK_6_2_2_lin.zip into your $XILINX_EDK area.

2

Issues Fixed by 6.2 EDK Service Pack 2

6.1i EDK, EDK_PlatGen - Maximum break points results in "ERROR:Xst:787 - Index value <16> is not in Range of array <which_pc>".
Please see (Xilinx Answer 18654).

6.2 EDK - MicroBlaze reset does not clear MSR register.
Please see (Xilinx Answer 19579).

6.1 EDK - Simulation of MicroBlaze fails when the target device is a Spartan-IIE.
Please see (Xilinx Answer 19580).

6.2 EDK, LibGen - "Compiling bsp boot.S: warning (dcc:1649): number after -O ignored when Diab is used."
Please see (Xilinx Answer 19585).

6.2 EDK, Base System Builder (BSB) - ML300 signal connections are incorrect for PCI.
Please see (Xilinx Answer 19291).

6.2 EDK - Cannot assign interrupt handler for GPIO driver.
Please see (Xilinx Answer 19586).

6.2 EDK - "HDL Parser error detected" reported in the final stage of Import Peripheral Wizard.
Please see (Xilinx Answer 19305).

6.2 EDK - ChipScope VIO core errors out during synthesis.
Please see (Xilinx Answer 19330).

6.2 EDK IP Wizard - Simulator compiling problem with IP wizard templates when not using version ID.
Please see (Xilinx Answer 19335).

6.2 EDK - Incorrect MB-GCC calculation.
Please see (Xilinx Answer 19587).

6.2 EDK - Simulation of a processor systems containing ChipScope cores fails.
Please see (Xilinx Answer 19588).

6.2 EDK SP1 - LwIP was included in Service Pack 1, but it does not work.
Please see (Xilinx Answer 19403).

6.2 EDK - The FIT timer does not generate an Interrupt output.
Please see (Xilinx Answer 19421).

6.2 EDK - The RevUp32to61 tool is missing a file that is necessary for it to run.
Please see (Xilinx Answer 19457).

EDK 6.2 - MAP errors with the chipscope_OPB_IBA on Spartan-3.
Please see (Xilinx Answer 19459).

6.2 EDK - XilFatFS linker error: "(writer.o): In function `_write_r' ... undefined reference to 'write'".
Please see (Xilinx Answer 19563)

6.2: EDK - What are the SDA_T and SCL_T signals in the OPB-IIC core?
Please see (Xilinx Answer 19175)

6.2 EDK SP1 - PLB_GPIO does not generate interrupts, ISR register returns unknown when read during simulation.
Please see (Xilinx Answer 19417)

6.2 EDK, LibGen - xintc_intr.c:122: 'XPAR_INTC_SINGLE_DEVICE_ID' undeclared.
Please see (Xilinx Answer 19303)

6.2 EDK OPB_PCI - How can I use less than six Block RAMs with OPB_PCI?
Please see (Xilinx Answer 19127)

IP Related Issues Addressed in Service Pack 2

OPB _Ethernet - Phy_Read always reports success even if Phy address is incorrect.
Please see (Xilinx Answer 19620)

OPB PCI Arbiter should default the park register to a valid value.
Please see (Xilinx Answer 19618)

PLB_ethernet - Timing problem possible with transmit status or receive length register reads.
Please see (Xilinx Answer 19619)

PLB_ZBT - Incorrect timing of MEM_RW_N signal causes writes to ZBTs to fail.
Please see (Xilinx Answer 19617)

Definition of ACTIVE, OBSOLETE, DEPRECATED and DELETE cores in proc_ip_ref_guide.
Please see (Xilinx Answer 19616)

6.1i EDK Documents - Request to have more information to explain the OPB ADDR range.
Please see (Xilinx Answer 19615)

OPB Emac Lite - PHY_tx_en might go active one clock cycle before first nibble valid.
Please see (Xilinx Answer 19607)

OPB Emac Lite - After collision, JAM might be omitted before SFD/preamble.
Please see (Xilinx Answer 19608)

OPB EMAC Lite - Frame might be incorrectly discarded as bad.
Please see (Xilinx Answer 19610)

OPB EMAC Lite - Frame incorrectly accepted if missing "End of Stream".
Please see (Xilinx Answer 19611)

PCI device driver Initialize() assumes device ID is zero.
Please see (Xilinx Answer 19612)

PCI I/O space decoding inconsistent.
Please see (Xilinx Answer 19613)

MicroBlaze - PC is not reset to zero after RST is issued in XMD.
Please see (Xilinx Answer 19614)

OPB_ethernetlite_v1_00_a inserts incorrect number of pad bytes.
Please see (Xilinx Answer 19606)

3

To simulate with NC-Sim, LDV 5.1-s012 or later is required.
AR# 19577
Date Created 06/21/2004
Last Updated 04/10/2007
Status Archive
Type General Article