We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19613

EDK PCI Core - I/O space decoding is inconsistent


General Description:  

The current implementation of the EDK PCI core has I/O space decoding behavior that is inconsistent with that described in Section of the PCI Specifications v2.3.  



"In the I/O Address Space, all 32 AD lines are used to provide a full byte address. The master that initiates an I/O transaction is required to ensure that AD[1::0] indicate the least significant valid byte for the transaction."  


Currently the two least significant bits of AD are not correct during a PCI I/O Space transaction. 



A byte write to I/O address 0x2ff currently results in AD=2fch and CBE=0111b on the PCI bus. 

Since AD[1:0] must indicate the least significant valid byte, the correct transaction should be AD=2ffh and CBE=0111h.


This problem is fixed in the latest 6.2 EDK Service Pack, available at: 

The first service pack containing the fix is EDK 6.2 Service Pack 2.

AR# 19613
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article