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AR# 19665

6.2i SP3 XST - XST generates wrong logic with VHDL statement "if xxx/=0 then"

Description

Keywords: XST, if, elsif, else, set, Behavioral, Post-translate, netlist, clear, synchronous

Urgency: Hot

General Description:
When a counter is controlled by a combination of synchronous clear, set, constant load and count enable in the same process, the behavioral simulation is different from the Post-Translate simulation indicating that XST produced incorrect logic during synthesis.

The code below represents VHDL code that XST will synthesize incorrectly:

Example:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity LTI_Gen is
generic (LTI_Time : INTEGER := 90) ;
port (
Clk: in STD_LOGIC; -- DVP_Clk (40MHZ)
CLR_n: in STD_LOGIC; -- Reset
LTI_En: in STD_LOGIC; -- LTIEnable
LTI_Tick: in STD_LOGIC; -- ClkEn
LTI_CamTr: out STD_LOGIC;
Debug: out std_logic_vector(31 downto 0)
);
end LTI_Gen;

architecture LTI_Gen_arch of LTI_Gen is

signal LTI_CamTr_i: std_logic;

begin

pLTI: process (CLK)
variable LTI_Cnt: integer range 0 to LTI_Time/10-1;
begin
if CLK'event and CLK='1' then
if CLR_n='0' or LTI_En='0' then
LTI_Cnt := 0;
LTI_CamTr_i <= '0';
else
if LTI_Tick='1' then
if LTI_Cnt/=0 then
LTI_Cnt := LTI_Cnt-1;
LTI_CamTr_i <= '1';
else
LTI_Cnt := LTI_Time/10-1;
LTI_CamTr_i <= '0';
end if;--LTI_Cnt
end if;--LTI_Tick
end if;--CLR_n
end if; -- CLK
end process pLTI;

LTI_CamTr <= LTI_CamTr_i;
Debug(0) <= LTI_En;
Debug(1) <= LTI_Tick;
Debug(2) <= LTI_CamTr_i;
end LTI_Gen_arch;

Solution

To work around this issue, change the if XXX /= 0 to "if xxx =0 then" and swap the content of the if and the else statement.
See the example below.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity LTI_Gen is
generic (LTI_Time : INTEGER := 90) ;
port (
Clk: in STD_LOGIC; -- DVP_Clk (40MHz)
CLR_n: in STD_LOGIC; -- Reset
LTI_En: in STD_LOGIC; -- LTIEnable
LTI_Tick: in STD_LOGIC; -- ClkEn
LTI_CamTr: out STD_LOGIC;
Debug: out std_logic_vector(31 downto 0)
);
end LTI_Gen;

architecture LTI_Gen_arch of LTI_Gen is

signal LTI_CamTr_i: std_logic;

begin

pLTI: process (CLK)
variable LTI_Cnt: integer range 0 to LTI_Time/10-1;
begin
if CLK'event and CLK='1' then
if CLR_n='0' or LTI_En='0' then
LTI_Cnt := 0;
LTI_CamTr_i <= '0';
else
if LTI_Tick='1' then
if LTI_Cnt = 0 then
LTI_Cnt := LTI_Time/10-1;
LTI_CamTr_i <= '0';
else
LTI_Cnt := LTI_Cnt-1;
LTI_CamTr_i <= '1';
end if;--LTI_Cnt
end if;--LTI_Tick
end if;--CLR_n
end if; -- CLK
end process pLTI;





LTI_CamTr <= LTI_CamTr_i;

Debug(0) <= LTI_En;
Debug(1) <= LTI_Tick;
Debug(2) <= LTI_CamTr_i;

end LTI_Gen_arch;

AR# 19665
Date Created 07/14/2004
Last Updated 07/18/2007
Status Archive
Type General Article