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AR# 19689

PLB/OPB DDR - Unbuffered DDR SDRAM DIMMs do not function correctly

Description

General Description:

A board with an unbuffered DDR SDRAM DIMM does not work as expected.

Solution

In order for the DDR SDRAM DIMM to recognize an operation, it must sample the DDR address and control signals on the rising edge of the input clock (otherwise known as the crossing point of the rising edge of DDR_Clk and the falling edge of DDR_Clkn).

Vendors of DDR SDRAM specify the setup (Tsu) and hold (Th) on the DDR address and control signals. Typically, these values are in the range of 0.7ns to 1.2ns depending on the input signal rise/fall time.

Virtex-II Pro designs utilizing the PLB or OPB DDR controller will register the DDR address and control signals on the rising edge of the system clock. The DDR output clock is generated with the 90 degrees phase shift of the system clock. With this design, the setup time on the DDR SDRAM is 0.25 * the system clock frequency; for example, if running at 100 MHz this equates to a setup time of 2.5 ns.

Timing Diagram

This setup time of 2.5 ns will change in actual hardware implementation. Board factors such as FPGA clock to output time, PCB trace length delay, and board components such as resistance and capacitance must be taken into consideration. Since the DDR clock/address/control signals all incur the FPGA clock to output time and PCB trace length delay, this factor can be eliminated when calculating actual board setup time at the DDR SDRAM DIMM.

All DDR clock/address/control signals from the FPGA are identically terminated with SSTL2_I. In this termination scheme, a series resistance (typical value = 50 ohms) and a parallel termination to Vt (typical value = 50 ohms) is included to reduce signal reflections.

Registered DDR SDRAM DIMMs include a register stage on all DDR address and control signals in the DIMM. Once the signals are registered, they are then routed to each DDR SDRAM device on the DIMM. In registered DIMMs, the device loading seen by the address and control signals is minimal.

In unbuffered DDR SDRAM DIMMs, the DDR address and control signals are not registered on the DIMM. They are routed directly from the DIMM pin to all the DDR SDRAM devices on the DIMM. With unbuffered DIMMs, the load seen by the DDR address and control signals is much greater than with a registered DIMM. This load is represented as the DIMM input capacitance on the DDR address and control signals.

Scope Shot

The value of DIMM input capacitance is critical to meeting the timing requirements associated with DDR SDRAM. With a large input capacitance, a slower signal rise or fall time will be observed vs. a DIMM with a smaller input capacitance value.

A designer can easily calculate the slew rate for the DDR address and control signals. If the DIMM vendor specifies an input capacitance of 24pF, the RC time constant is (24 pF) * (50 ohms) = 1.2 ns. With another DIMM vendor, the input capacitance could be in the range of 126 pF. This RC time constant is (126 pF) * (50 ohms) = 6.3 ns.

Unbuffered DIMM DDR SDRAM device loading does not effect the DDR clock signals. Most unbuffered DIMM vendors require multiple clock pairs (to reduce signal loading), where each clock pair drives only a percentage of the DDR SDRAM devices on the DIMM.

The following scope shot illustrates the slow transition times when utilizing an unbuffered DIMM with 126pF input capacitance on the DDR address and control signals.

Looking closer at the scope shot here illustrates the transition time for DDR_WEn and DDR_ADDR[2]. The dotted cursor line illustrates the rising edge of DDR_Clk. At this time, the DDR_WEn control signal is transitioning to logic level 0. At the rising edge of DDR_Clk, DDR_WEn is still transitioning to a Vil value and the setup time on the DIMM is not guaranteed.

Additional analysis with HyperLynx allows board level simulation. Modeled in this simulation is a Virtex-II Pro SSTL2_I I/O driver toggling an output at 50 MHz. The V2P I/O driver is connected to a 50 ohm 4" transmission line with a 50 ohm pullup resistor to 1.25V and a capacitor connected to ground. The wave window shown below illustrates the signal properties with a) 24 pF and b) 126 pF lumped capacitance connected to ground. A slow transition time of ~ 5ns (Vil to Vih) is observed on the trace with 126pF, while a fast (less than 1ns) transition time is seen for the trace with 24pF loading.

Simulation with 24pF load

In conclusion, make sure timing analysis is performed on all DDR signals if using unbuffered DDR SDRAM DIMMs. If DDR address and control signals setup and hold times are not met, the command to execute will not be recognized by the memory device(s). If possible, the more reliable solution is utilizing a registered DDR SDRAM DIMM.

For more information on DDR timing calculations, see (Xilinx Answer 19385).

AR# 19689
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article