When I generate my design using Base System Builder in XPS for the Spartan-3 Starter Kit board, the following error message occurs during synthesis (generate netlist):
* HDL Compilation *
Compiling vhdl file C:/CASES/S3_STARTER_BUG/hdl/system.vhd in Library work.
ERROR:HDLParsers:1401 - C:/CASES/S3_STARTER_BUG/hdl/system.vhd Line 766. Object SRAM_256Kx32_Mem_CEN of mode OUT can not be read.
Total memory usage is 50224 kilobytes
The signal connection (CEN) is incorrect for the SRAM. The Error in PlatGen occurs when the system is not the top level of the design.
The MHS file declares the 2 output PORTS for the CEN (These two ports are needed for 2 x 16 Bit SRAMs on the board).
PORT SRAM_256Kx32_Mem_CEN = SRAM_256Kx32_Mem_CEN, DIR = output, VEC = [0:0]
PORT SRAM_256Kx32_1_Mem_CEN = SRAM_256Kx32_Mem_CEN, DIR = output, VEC = [0:0]
And at the OPB_EMC controller the CEN signal gets connected with both PORT CEN signals
PORT Mem_CEN = SRAM_256Kx32_Mem_CEN
The problem now is the generated VHDL code (please review the system.vhd for details)."
You can work around this problem as follows:
1. Create an internal signal in MHS for connecting the EMC Mem_CEN to the PORT SRAM_256Kx32_Mem_CEN and to the PORT SRAM_256Kx32_1_Mem_CEN (as shown below). Modify the MHS file to include the following changes:
PORT SRAM_256Kx32_Mem_CEN = i_SRAM_256Kx32_Mem_CEN, DIR = output, VEC = [0:0]
PORT SRAM_256Kx32_1_Mem_CEN = i_SRAM_256Kx32_Mem_CEN, DIR = output, VEC = [0:0]
2. At the OPB_EMC controller, make these changes:
PORT Mem_CEN = i_SRAM_256Kx32_Mem_CEN