Solution

1

IP
For Virtex-4 IP and CORE Generator-related Known Issues, refer to (Xilinx Answer 20486), (Xilinx Answer 20491), and (Xilinx Answer 21135).

NOTE: The following issues are being investigated and will be fixed in a future software release.

PACE
7.1i PACE Virtex-4 - DSPs and FIFOs are included in the Area Group, when not in the design. See (Xilinx Answer 19934) for more information.

EDK
7.1i EDK - PLB/OPB DDR Cores fail to meet timing when running at 100 MHz in Virtex-4 devices. See (Xilinx Answer 21218) for more information.

Data2MEM
7.1 Data2MEM - Data2MEM issues a segmentation fault for some Virtex-4 devices. See (Xilinx Answer 20901) for more information.

NOTE: The following issues have been fixed or updated in ISE 8.1i.

FIXES:
XST
XST grounds the unused upper address bit of a block RAM.

Simulation
DSP48 model asserts the following warning: "Warning OPMODE 0000101 with CARRYINSEL 00 to DSP48 instance is invalid."

NOTE: The following issues have been fixed or updated in ISE 7.1i Service Pack 4.

FIXES:
iMPACT

iMPACT will not program a Virtex-4 if it is the only device in the chain.

An iMPACT-generated JTAG programming file (SVF/XSVF/System ACE CF) does not program a Virtex-4 device.

2

NOTE: The following issues have been fixed or updated in ISE 7.1i Service Pack 3.

UPDATES:
BitGen
Bitstream encryption is supported for Virtex-4.

FIXES:
BitGen
DCI I/O not working. Outputs set to DCI do not output correct logic and the I/O seems to be disabled.

MAP
"FATAL_ERROR:Pack:pksbamergeset.c:573:1.22.14.1" occurs during the packing phase.

MAP will fail with an error if an OBUFTDS symbol is configured with a constant input.

In a design using DSP48, "ERROR:LIT:382" occurs if -timing is used.

PartGen
The pad name runs into the pin name on Virtex-4 FX partgen output.

Simulation
The write process in the Dynamic Reconfiguration does not work during a simulation of the DCM_ADV.

3

NOTE: The following issues have been fixed or updated in ISE 7.1i Service Pack 2.

FIXES:
Floorplanner
BUFRs are located in the center I/O column.

Simulation
The IDELAY component does not show any delays at the output during a timing simulation.

The S and R value is left unconnected on the ODDR, which causes timing simulations to fail.

iMPACT
Virtex-4 configuration fails when using a serial download or PROM configuration with an MCS file generated by 7.1i iMPACT.

IBISWriter
The LVDSEXT_25 IBIS model generated by IBISWriter for a Virtex-4 design shows a differential signal swing that is reduced approximately 20 percent from the same model for Virtex-II and Virtex-II Pro.

MAP
Multiple placement issues with DSP48.
Post-MAP simulation problem affecting DSP48s.

PAR
Beginning with version 7.1i, the I/O placer creates internal macros to better handle the automatic placement of LVDS pairs. This new macro causes problems if the designer LOCs the Master IOB to the Slave site and vice versa.

4

NOTE: The following issues have been fixed or updated in ISE 7.1i Service Pack 1.

UPDATES:
To use the DCM in High-Frequency mode, 7.1i SP1 must be used. See (Xilinx Answer 20529) for more information.

HSTL_I_12 support added.

Package Files
Package files for Virtex-4 devices have been updated.

XPower
Support for LX and SX devices has been added.

FIXES:
Constraints Editor
Incorrect voltage range shown for VCCINT.

Simulation
When running a SmartModel simulation with more than one GT11 SmartModel in the simulators, the simulators fail.

5

NOTE: The following issues are addressed in ISE 6.3i Service Pack 3.

Package File
- The pin-out for the FF1152 package (available for FX only) has changed.
- The Virtex-4 Packaging Specifications version v1.3 and later reflect the latest pin-out for FX40 and FX60.
- Version v2.0 and later reflect the latest pin-out for FX100.

Virtex-4 User Guides -> Virtex-4 Packaging Specifications
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/User+Guides/FPGA+Device+Families/Virtex-4/&iLanguageID=1

NOTE: The following issues will be addressed in ISE 6.3i Service Pack 2.

Primitives/Components Specific
- BUFR with multi-clock regions is not supported: ISE 6.3i attempts to place everything driven by a BUFR in one clock region. If a BUFR fans out to more resources than contained in one clock region, PAR errors out. The area constraint or clock region constraint is NOT obeyed.
- DCM- PMCD: PAR does not use the dedicated routes from the DCM to the clock inputs of the PMCD. Currently, these routes must be manually routed in the FPGA Editor. The dedicated routes must be used to achieve phase matching.



NOTE: The following issues have been fixed in the 6.3i Service Pack 1.

Simulation
- Many important updates related to simulation models are added to ISE 6.3i Service Pack 1.

XST
- XST might incorrectly infer BUFG on nets driven by BUFR and cause PAR to fail when routing clocks.

Primitives/Component Specific
- You must tie off unused ports on an instantiated DSP48.
- OSERDES is not set correctly when used with LVPECL or Complimentary Single-Ended (CSE) I/O Standard.
- DCM- PMCD: When using the DCM phase shift in Direct mode through the Dynamic Reconfiguration Port, clock rates below 100 MHz are not supported due to incorrect bit setting.
- FX family.
- Many GT11 updates (including automatic placement and DRCs).