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AR# 19726

6.3i NetGen, Timing Simulation - A simulator reports hold violations when simulating Virtex-4 designs with SRL16E components

Description

Keywords: timing, simulation, SimPrim, ERROR, ModelSim, NC-VHF, NC-Verilog, hold, error, Virtex-4, VCS

Urgency: Standard

General Description:
Back-annotated simulations of Virtex-4 designs containing SRL16E components report hold violations.

Solution

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19726
Date Created 09/03/2007
Last Updated 11/10/2008
Status Archive
Type General Article