Keywords: timing, simulation, SimPrim, ERROR, ModelSim, NC-VHDL, NC-Verilog, Virtex-4, VCS, SRTYPE, SYNC, ASYNC, ODDR, IDDR
Urgency: Standard
General Description:
The SRTYPE value is set to SYNC for ODDR and IDDR components, even though I changed this to ASYNC in the HDL code.