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AR# 19766

LogiCORE Endpoint for PCI Express - For the Virtex-II Pro, what are TX_PREEMPHASIS and TX_DIFF_CTRL set to, inside the PCI Express Core? Is this compliant?

Description

When using the LogiCORE Endpoint for PCI Express with the Virtex-II Pro device, what are TX_PREEMPHASIS and TX_DIFF_CTRL set to, inside the PCI Express Core? Is this compliant?

Solution

The LogiCORE Endpoint for PCI Express sets TX_PREEMPHASIS to 3, and TX_DIFF_CTRL to 500 mV. This means the first bit in a succession of like polarity bits being boosted because of pre-emphasis could reach a level of 1330 mV (500 mV * 2 + (33% of (500 mV *2)). Does this indicate a violation of the PCI Express specification?

The PCI Express specification in section 4.3.2.3 states the following:

De-emphasis must be implemented when multiple bits of the same polarity are output in succession. Subsequent bits are driven at a differential voltage level 3.5 dB (+/-.5 dB) below the first bit. Note that individual bits, and the first bit from a sequence in which all bits have the same polarity, must always be driven between the Min and Max values as specified by VTX-DIFFp-p in Table 4-5.

Table 4-5 shows that VTX-DIFFp-p or the Differential Peak-to-Peak Output Voltage ranges from a minimum of 800 mV to a maximum of 1200 mV.

The specification uses De-emphasis to ensure a clean waveform. This means that the second bit in a succession of like polarity bits is driven at a level 3.5 dB below the first.

In the Virtex-II Pro device, the first bit is boosted relative to the second bit using pre-emphasis. Pre-emphasis and de-emphasis have the same basic effect on the waveform. De-emphasis attenuates the low-frequency components of the signal, whereas Pre-emphasis boosts the high frequency components. But if the TX_DIFF_CTRL is set to 500 mV, the first bit could potentially be boosted to 1330 mV.

The actual value of the signal at the near end will depend on more than the settings of the TX_PREEMPHASIS attribute setting. They are also a function of the trace length, width, and material; essentially, how much the TX driver is loaded.

Xilinx does not instruct users of PCI Express on how to lay out the boards as far as the trace topology and stackup is concerned. Because of this, the PCI Express Core TX_PREEMPHASIS and TX_DIFF_CTRL setting might not work in every case. Users of the PCI Express Core must calculate the value for TX_PREEMPHASIS and TX_DIFF_CTRL for their board to work properly. Users must ensure that the settings used will allow for a clean waveform, as described in Chapter 4 of the PCI Express Base Specification.

Users can modify the settings of TX_PREEMPHASIS and TX_DIFF_CTRL, either by using FPGA Editor or adding constraints to the UCF file.

FPGA Editor

1. Open the placed and routed design in FPGA Editor.

2. Locate the MGT(s) being used for the PCI Express 1-lane or 4-lane core and double-click it to view the attributes of the MGT.

3. Change the FPGA Editor mode to Read/Write so that the attributes can be modified.

4. Change the value of TX_PREEMPHASIS and TX_DIFF_CTRL to the desired setting.

5. Save the NCD file and run bitgen on this file. Changing this value in FPGA Editor is convenient if implementation time is lengthy. For more information on using the FPGA Editor, refer to the Xilinx ISE Design Tools Manuals.

UCF Constraints

Add the following to the 1 Lane PCI Express Core UCF file:

INST "pci_exp_ep/plm/mgt/GST0" TX_PREEMPHASIS = "0 or 1 or 2 or 3";

INST "pci_exp_ep/plm/mgt/GST0" TX_DIFF_CTRL = "400 or 500 or 600 or 700 or 800";

For the 4-Lane Core, add the following to the UCF file:

INST "pci_exp_ep/plm/mgt/GST0" TX_PREEMPHASIS = "0 or 1 or 2 or 3";

INST "pci_exp_ep/plm/mgt/GST1" TX_PREEMPHASIS = "0 or 1 or 2 or 3";

INST "pci_exp_ep/plm/mgt/GST2" TX_PREEMPHASIS = "0 or 1 or 2 or 3";

INST "pci_exp_ep/plm/mgt/GST3" TX_PREEMPHASIS = "0 or 1 or 2 or 3";

INST "pci_exp_ep/plm/mgt/GST0" TX_DIFF_CTRL = "400 or 500 or 600 or 700 or 800";

INST "pci_exp_ep/plm/mgt/GST1" TX_DIFF_CTRL = "400 or 500 or 600 or 700 or 800";

INST "pci_exp_ep/plm/mgt/GST2" TX_DIFF_CTRL = "400 or 500 or 600 or 700 or 800";

INST "pci_exp_ep/plm/mgt/GST3" TX_DIFF_CTRL = "400 or 500 or 600 or 700 or 800";

Constraints in the UCF file will override the default settings inside the core.

For more information on the meaning of the TX_PREEMPHASIS and TX_DIFF_CTRL settings, refer to the Virtex-II Pro RocketIO Transceiver User Guide.

AR# 19766
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article