Designs that simulate correctly in older versions of NC-VHDL (3.4 and below) do not work in the newer version of the tools. When debugging further, I discover that the X_FF in the design does not come out of reset.
This is a problem in the algorithm that does the Xilinx Library Acceleration. Recent changes made to the Xilinx libraries cause this algorithm to fail.
To work around this problem, use the -noxilinxaccl switch in the ncelab command line.
This issue has been fixed in the following versions of NC-Sim:
LDV 5.0 S24 and above
LDV 5.1 S16 and above
IUS 5.3 S6 and above