UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19839

7.1i ISE - Project Navigator is closed down every time a source file is saved

Description

Keywords: ISE, 6.2, SP3, Verilog, project, close, recursive, loop

Every time any file in a Verilog project is saved, the ISE Project Navigator closes. If launched again, Project Navigator can successfully open the same project. The latest modifications have been saved, and the design can be implemented. However, if the design files are saved again, Project Navigator closes down again.

No error message or warning is given when the software exits.

How can I solve this problem?

Solution

This behavior has been seen to be caused by Verilog module(s) defined in the top-level file of the project, but instantiated into a file on a lower level.

To solve the problem, you can either:

1. Cut and paste the module(s) definition into the same file(s) they are being instantiated in.

or

2. Save each module definition into a separate file and then add the resulting files into the project.
AR# 19839
Date Created 08/20/2004
Last Updated 12/12/2006
Status Archive
Type General Article