Keywords: NetGen, timing, simulation, ERROR, error, Virtex-4, DCM, RST, 3, clock
Urgency: Standard
General Description:
When I running a timing simulation, the following error appears, even when Reset has been asserted for more than three clock cycles:
"# Input Error : RST on instance <instance_name> must be asserted for 3 CLKIN clock cycles."
This also causes the DCM not to lock.