Keywords: SimPrim, VHDL, timing, simulation, ModelSim, NC-VHDL, TXRUNDISP, X_GT10, Rocket-IO
Urgency: Standard
General Description:
When a timing simulation is performed, the following discrepancies between UniSim- and SimPrim-based models occur:
1. TXRUNDISP goes to X after some time.
2. RXDISPERR and RXNOTINTABLE go to X after TXOUTCLK starts.
3. PMARXLOCK goes High-Low very frequently.