Keywords: UniSim, simulation, ModelSim, NC-VHDL, ISERDES, IDELAY, Virtex-4, VHDL, swallow, pulse
Urgency: Standard
General Description:
When the tap delay of the ISERDES (IDELAY Module) is increased to a large value, the UniSim's VHDL IDELAY module begins to swallow small input pulses to the ISERDES.