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AR# 19857

6.3i UniSim, Simulation - When the tap delay of the ISERDES (IDELAY Module) is increased to a large value, the IDELAY module begins to swallow small input pulses to the ISERDES (VHDL)

Description

Keywords: UniSim, simulation, ModelSim, NC-VHDL, ISERDES, IDELAY, Virtex-4, VHDL, swallow, pulse

Urgency: Standard

General Description:
When the tap delay of the ISERDES (IDELAY Module) is increased to a large value, the UniSim's VHDL IDELAY module begins to swallow small input pulses to the ISERDES.

Solution

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19857
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article