Keywords: UniSim, simulation, ModelSim, NC-Verilog DCM, lock, VCS, Verilog
Urgency: Standard
General Description:
DCM does not lock during Verilog simulation when the CLKIN is "1" at time 0. This problem can be seen when simulating the reference design in (
Xilinx XAPP677): "300-Pin MSA Bit-Error Rate Tester for the ML10G Board and RocketPHY Transceiver."