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AR# 19859

6.3i UniSim, Simulation - DCM does not lock during Verilog simulation when the CLKIN is "1" at time 0 (XAPP677)

Description

Keywords: UniSim, simulation, ModelSim, NC-Verilog DCM, lock, VCS, Verilog

Urgency: Standard

General Description:
DCM does not lock during Verilog simulation when the CLKIN is "1" at time 0. This problem can be seen when simulating the reference design in (Xilinx XAPP677): "300-Pin MSA Bit-Error Rate Tester for the ML10G Board and RocketPHY Transceiver."

Solution

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19859
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article