Keywords: UniSim, simulation, ModelSim, NC-VHDL, DCM, Virtex-4, VCS, CLKFX, align, locked
Urgency: Standard
General Description:
The Virtex-4 DCM and output clocks (CLK0, CLk2x, CLKDV and CLKFX) are not aligned correctly. The rising edges of these outputs should be aligned, but CLKFX starts one input clock cycle early; therefore, the CLKFX edge is not correctly aligned when the locked signal goes High.