We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19861

6.3i UniSim, SimPrim, Simulation - Virtex-4 DCM CLKFX is not properly aligned when Locked signal goes high


Keywords: UniSim, simulation, ModelSim, NC-VHDL, DCM, Virtex-4, VCS, CLKFX, align, locked

Urgency: Standard

General Description:
The Virtex-4 DCM and output clocks (CLK0, CLk2x, CLKDV and CLKFX) are not aligned correctly. The rising edges of these outputs should be aligned, but CLKFX starts one input clock cycle early; therefore, the CLKFX edge is not correctly aligned when the locked signal goes High.


This problem has been fixed in the latest 6.3i Service Pack available at:
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19861
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article