When using DriveDONE on the last device in a Serial daisy chain of FPGAs (Virtex-II, Virtex-II Pro, Virtex-4, or Spartan-3) with the FPGA DONE connected to the PROM's CE signal, FPGAs in the chain might not start up and function.
If the last device in the daisy chain is set to DriveDone, there will be contention between the last device and the beginning devices for a short period of time (~100 us). This is because the last FPGA releases the DONE and starts up while the FPGAs in the beginning of the chain have not released the DONE pin. When the last device in the chain releases the DONE signal, the PROM's CE signal with the contention is read at ~1.5V and registered as a High. This disables the PROM and prevents the startup sequence from being completed on the device.
You can work around this issue by disconnecting the PROM's CE and grounding this signal to activate the PROM and prevent the disabling from happening early.
Use an external pull-up on the DONE signal (as shown in the appropriate PROM data sheet) and not the DriveDONE BitGen option.