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AR# 19869

Virtex-II Pro Data Sheet - What is the value for TICCK (CCLK output delay)?


General Description: 

The value for TICCK is missing in the Virtex-II Pro Data Sheet - DS083 (v4.0) June 30, 2004. What does this value represent? Why is this value missing?


In master mode configuration, the FPGA sends CCLKs to the PROM during configuration. TICCK represents the delay between INIT going High and the output of CCLK. 



0.250 us min  

4.000 us max

AR# 19869
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article