This Answer Record contains the following information for the LogiCORE Gigabit Ethernet MAC v5.0 Core, which is released in 6.3i IP Update 3 and IP Update 4:
- What's New
- Known Issues
NOTE: The Gigabit Ethernet MAC v5.0 Core is identical in both 6.3i IP Update 3 and IP Update 4 releases.
- Support added for Virtex-4.
- Added a Reduced Gigabit Media Independent Interface (RGMII), which is an alternative to the Gigabit Media Independent Interface (GMII).
- The core was simplified by removing the 1000BASE-X output option (this functionality is now supported in a separate core, the Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE, which you can instantiate separately).
- The core was simplified by removing support for Half Duplex mode (this includes the removal of the gmii_col and gmii_crs signals).
- A synthesisable Example Design has been added, complete with new demonstration testbench.
- Support added to the Transmitter and Receiver Statistics Vectors to count jumbo frames up to 16384 bytes in length (this makes the Statistic Vectors non-backwards compatible with previous versions).
- Management blocks enhanced to use clock enables rather than using the MDC clock on local routing.
- UCF file improvements.
- New documentation has been added, including Getting Started Guide and User Guide.
- Fixed an issue in which Undersize and Fragment statistics incremented incorrectly when implemented in block RAM.
1. Table 16 of the data sheet incorrectly states the LUT utilization numbers for the first RGMII row as 154. The correct value should be 1540.
2. The Tx Byte Valid bit (Bit 20) of the tx_statistics_vector is stuck at ground. For more information on this issue, see (Xilinx Answer 20381). To resolve this issue, install the patch below and regenerate the core.
3. There may be excessive delay between tx_data_valid and tx_ack when transmitting jumbo frames when jumbo frame support is disabled. For more information on this issue, see (Xilinx Answer 20741).
4. The RGMII interface should use HSTL as its IOSTANDARD, instead of LVTTL, since it is designed according to the RGMII v2.0 specification. To work around this issue, change the IOSTANDARD in the ".ucf" file accordingly. For more information on this issue, see (Xilinx Answer 21324).
To resolve issue #2 from above, apply the appropriate patch below for the ISE version that you are using:
* For 7.1i installation, use the following patch:
If the following patch was installed for the 6.2.03i IP Update 3 or 6.3i IP Update 4 installation and then 7.1i was installed, you must install the above patch to the 7.1i installation as well.
* For 6.2.03i IP Update 1.2 or 6.3i IP Update 4 installation, use the following patch:
If the patch was installed for the 6.3i IP Update 3 version of the core and then IP Update 4 was installed, you must re-install the patch. This is necessary because IP Update 4 does not contain the fixes and installing it will overwrite the patched files.
Install the patch as follows:
1. Unzip the contents of the ".zip" file or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You might need to have system administrator privileges to install the patch.
2. After installing the patch, regenerate the Gigabit Ethernet MAC Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.