This Answer Record contains the following information for the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 Core, which is released in 6.3i IP Update 3 and IP Update 4:
- What's New
- Known Issues
NOTE: The Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 core is identical in both 6.3i IP Update 3 and IP Update 4 releases.
- Support added for Virtex-4 (Ten-Bit-Interface (TBI) option only).
- In addition to supporting the 1000BASE-X standard, the core can optionally be generated to behave as a Gigabit Media Independent Interface (GMII) to Serial-GMII (SGMII) bridge.
- RocketIO Transceiver instances are removed from the core, and you must now instantiate them to allow more flexibility (the HDL example design provided with the core provides an example RocketIO instantiation).
- Auto-Negotiation support enhanced, including a programmable Link Timer.
- UCF file improvements.
- Demonstration testbenches enhanced to include 8B10B encoding and decoding procedures.
- New documentation has been added, including Getting Started Guide and User Guide.
- Corrected an issue in which occasional frame loss occurred when using the TBI interface.
1. The definition of the configuration_vector[3:0] is incorrect in Table 4 of the Data Sheet and Table 8-22 of the User Guide. Specifically, the pin mapping is currently as follows:
Bit [3:2] => Loopback Control
Bit  => Power Down
Bit  => Isolate
The correct ordering is as follows:
Bit  => Reserved
Bit  => Loopback Control
Bit  => Power Down
Bit  => Isolate
The Data Sheet and User Guide is fixed in IP Update 4. If using IP Update 3, the updated Data Sheet and User Guide are posted on the Ethernet 1000BASE-X PCS/PMA or SGMII lounge Web page and can be reached from these links:
The updated Data Sheets and User Guide will have this fix added to the revision history. In addition, the date at the bottom of each page will now be October 11, 2004.
2. The Verilog demonstration testbench (demo_tb.v) uses incorrect array sizes that cause only a portion of the frames to be transmitted and received. For more information on this issue, see (Xilinx Answer 20239). To resolve this issue, install the patch below and regenerate the core. The new testbench will include the fixes for the proper array sizes.
3. Incorrect alignment when "MGT CRC Enabled" is used results in incorrect IDLE generation. For more information on this issue, see (Xilinx Answer 20240). To resolve this issue, install the patch below and regenerate the core. The new "transceiver.vhd" and "transceiver.v" files will properly align the data as a work-around to this issue.
To resolve issues #3 and #4 from above, apply the appropriate patch below for the version of ISE that you are using:
* For 7.1i installation, use the following patch:
If the following patch was installed for the 6.2.03i IP Update 3 or 6.3i IP Update 4 installation and then 7.1i was installed, you must install the above patch to the 7.1i installation as well.
* For 6.2.03i IP Update 1.2 or 6.3i IP Update 4 installation, use the following patch:
If the patch was installed for the 6.3i IP Update 3 version of the core and then IP Update 4 was installed, the patch will need to be reinstalled. The reason is that IP Update 4 does not contain the fixes and installing it will overwrite the patched files.
Install the patch as follows:
1. Unzip the contents of the ".zip" file or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You might need to have system administrator privileges to install the patch.
2. After installing the patch, regenerate the Ethernet 1000BASE-X PCS/PMA or SGMII core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.