We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19938

6.3i ChipScope Pro - When I try to probe a DDR register in ChipScope Core Inserter, I get unrouted nets


General Description: 

When I try to use the ChipScope Core Inserter to utilize FDDRCPE registers as a Trigger or Data, PAR completes but there are unrouted nets in FPGA Editor and my DDR registers are not implemented in the I/O blocks (IOBs).


The FDDRCPE primitive should be grayed out and unavailable for selection in the ChipScope Core Inserter. The IOBs do not allow ChipScope access to the output of the DDR registers, and, as a result, they cannot be probed using ChipScope.

AR# 19938
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article