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AR# 19943

14.x Timing - Why does Timing Analysis report a clock skew that does not match the MAXSKEW constraint?

Description

When running Timing Analyzer on my design with local clocks, I receive an internal hold violation because of the calculated skew.

The calculation seems to be incorrect based on a MAXSKEW report that shows that the skew on the net is smaller.

Solution

Timing Analysis is using the relative minimum for a portion of the clock path.

The skew calculation is using a common driver analysis.

The timing analysis engine finds the common driver between the clock path to the source and the clock path to the destination, and calculates the clock skew from that point.
AR# 19943
Date Created 09/03/2007
Last Updated 03/11/2015
Status Active
Type Known Issues
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3
  • ISE Design Suite - 14.4
  • ISE Design Suite - 14.5
  • ISE Design Suite - 14.7
  • Less