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AR# 19945

6.3i Architecture Wizard - Incorrect HDL generated for DCM/PMCD when DCM CLKDV clock is connected to PMCD CLKA

Description

General Description: 

Incorrect HDL is generated for DCM/PMCD usage. The signal between the DCM CLKDV port and the PMCD CLKA port is not connected properly.

Solution

This problem has been fixed in the latest 6.3i Service Pack available at: 

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.

AR# 19945
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article