Spartan-3/-3E/-3A - What are the BUFGMUX placement rules and global clock routing restrictions?

AR#	19947	Search For Another Answer
Topic	CLB/Routing
Last Updated	10/27/2011
Status	Active

Description

What are the rules for placing BUGMUX components in Spartan-3/-3E? Should any routing restrictions be considered for global clocks?

Solution

In a BUFGCE or BUFGMUX configuration, shared inputs must be considered. Any two adjacent clock multiplexer pairs share I0/I1 inputs. This is true for both Spartan-3, Spartan-3E, and Spartan-3A devices.  

For example, if BUGMUX0 is connected to GCLK0 and GCLK1, then BUFGMUX1 also has the same I0/I1 and I1/I0 inputs. Figure 1 shows how the I0/I1 input pins are shared between adjacent clock multiplexers. 


Figure 1 - BUFGMUX shared inputs 

Spartan-3 does not use the primary/secondary clocking scheme that is used in Virtex-II/-II Pro. There are eight global clock buffers in Spartan-3 and eight global clock spines in each quadrant, so any BUFGMUX can route to any quadrant.  

Spartan-3E/-3A also do not use the primary/secondary clocking scheme; however, Spartan-3E/-3A use a new scheme that implements Left-Side Half, Right-Side Half, and All Quadrant global clocks.  

Spartan-3E/-3A have four All Quadrant BUFG global clocks on the top of the device and four All Quadrant BUFG global clocks on the bottom, for a total of eight in each device. All Quadrant BUFG global clocks can route to all regions in the device (Quadrant 1, 2, 3, or 4). 

There are also eight Left-Half BUFG and eight Right-Half BUFG semi-global clocks. The Left-Half BUFG can route only to loads in the left half of the device and the Right-Half BUFG can route only to loads in the right half. 

Any quadrant can have a maximum of eight clocks routed to it (out of the available 16 All Quadrant and Left/Right-Half clocks). Along with these global/semi-global clocks, additional local clocks can be used within the quadrants. 

In Figure 2 below, the matching color BUFGs represent clock buffers that share a common clock mux in their respective quadrants.  

For this example, Quadrant 1 has a solid red buffer indicating an All Quadrant BUFG and a red buffer with a white circle in it indicating a Left-Half BUFG. Since these two clocks share a common input to the clock mux for Quadrant 1, they cannot both drive loads in Quadrant 1.  

It is possible to route a clock signal driven by the solid red All Quadrant BUFG into Quadrant 1 and also use a black, blue, and green Left-Half BUFG in Quadrant 1. In this same scenario, it is also possible to route clocks driven by the Left-Half BUFGs in Quadrant 3 into Quadrant 1. 

It is also possible to route a clock signal driven by the red All Quadrant BUFG into Quadrant 1 and then use the red Left-Half BUFG to route to loads in Quadrant 3.  

Note: The Spartan-3A XC3S50A does not have this mux structure and so for this smaller device the Side BUFG and Top/Bottom BUFG of the same color cannot have loads on the same side (Left/Right) of the device without one of the clock nets leaving the global routing resources.


Figure 2- Spartan-3E side BUFGs 

For more information, see the "Using Global Clock Resources" chapter in the Spartan-3 Generation FPGA User Guide (UG331).