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AR# 19953

9.1 Incremental Design - XST gives "ERROR:HDLCompilers:27" when top-level module has HDL black boxes


Keywords: incremental, design, Project, Navigator, XST, error

When running Incremental Synthesis on a Verilog module that contains both a black box instantiation and 'incremental_synthesis' / 'resynthesize' constraints in the XCF, the following errors occur:

"ERROR:HDLCompilers:27 - top.v line N Illegal redeclaration of 'A' Module <A> compiled."

"ERROR:16- top.v line N. The module "A" conflicts with a previously defined module of the same name. The definition must be resolved before the processes will be available for the source."



These errors occur because XST reads other modules to detect logic changes after HDL compilation, HDL Analysis, and HDL Inference of all blocks.

To work around this issue, comment out or remove the top-level black box definitions from "design.v".


Remove the other top-level module sources from top project and update XCF manually to indicate what module underwent logic changes.
AR# 19953
Date Created 09/03/2007
Last Updated 06/02/2009
Status Active
Type General Article