AR# 19956 6.3i Speed Files/Timing/Simulation Virtex-4 - Timing Analysis and SDF do not match for clock pad delay Tiopi

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Solution

General Description:

When I do a timing analysis and timing simulation, the clock pad delays do not match for my Virtex-4 design. This is also true for OSERDES in Virtex-4. When is this going to be fixed?

This problem has been fixed in the latest 6.3i Service Pack available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.

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AR# 19956
Date Created	09/03/2007
Last Updated	01/18/2010
Status	Archive
Type

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AR# 19956 6.3i Speed Files/Timing/Simulation Virtex-4 - Timing Analysis and SDF do not match for clock pad delay Tiopi

Description

Solution

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