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AR# 19972

Spartan-IIE/-3 - Simultaneous Switching Output (SSO) guidelines for LVDS and LVPECL


The Xilinx Application Note 179 (Xilinx XAPP179), "Using SelectI/O Interfaces in Spartan-II and Spartan-IIE FPGASs" does not include entries for LVDS and LVPECL. What is the recommended maximum number of SSOs for these signals?

Are there SSO guidelines for Spartan-3?


NOTE: For a detailed discussion on handling SSOs, see (Xilinx XAPP689): "Managing Ground Bounce in Large FPGAs."

For SSO guidelines, use these substitutions:

Spartan-IIE, LVDS: one output pair = one LVTTL 2mA driver with fast slew rate

Spartan-IIE, LVPECL: one output pair = one LVTTL 24mA driver with fast slew rate

The Spartan-IIE SSO guidelines are provided in (Xilinx XAPP179). Select "Design Considerations" -> "Simultaneous Switching Guidelines".

Because the Spartan-3 LVDS driver is very balanced, its switching causes a negligible amount of transient current. As a result, SSOs are typically not a problem in the smaller device/package combinations. However, SSO does become a concern with the larger device/package combinations so please be aware of the SSO guidelines for Spartan-3.

The Spartan-3 SSO guidelines are provided in the "Spartan-3 DC and Switching Characteristic" Data Sheet located at:


Select "Switching Characteristics" -> "Simultaneous Switching Output Guidelines".

AR# 19972
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article