Keywords: Verilog, parameter, passing, local
XST will not propagate a defparam to modify a parameter if the defparam spans multiple level of hierarchy and modifies multiple instantiations, as shown in the following example:
module top (...);
:
defparam u1.sub_inst.P1 = 1;
defparam u2.sub_inst.P1 = 2;
my_mod u1 (<port_mapping>);
my_mod u2 (<port_mapping>);
:
endmodule
//------------------------------
module my_mod (...);
SUB_MOD sub_inst (<port_mapping>);
endmodule
//------------------------------
module SUB_MOD (...);
parameter P1 = 0;
:
:
endmodule
//------------------------------