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AR# 19975

7.1i XST - "WARNING:Xst:2193 - "file.v" line xx: Defparam through hierarchy is partially supported and may give incorrect results. It is recommended that you avoid using this construct."

Description

Keywords: Verilog, parameter, passing, local

XST will not propagate a defparam to modify a parameter if the defparam spans multiple level of hierarchy and modifies multiple instantiations, as shown in the following example:

module top (...);
:
defparam u1.sub_inst.P1 = 1;
defparam u2.sub_inst.P1 = 2;

my_mod u1 (<port_mapping>);
my_mod u2 (<port_mapping>);
:
endmodule

//------------------------------

module my_mod (...);
SUB_MOD sub_inst (<port_mapping>);
endmodule

//------------------------------

module SUB_MOD (...);
parameter P1 = 0;
:
:
endmodule

//------------------------------

Solution

You can work around this issue by creating parameters on every level of hierarchy in order to modify the wanted parameter, as shown in the following example:

module top (...);
:

my_mod #(.mymod_param(1)) u1 (<port_mapping>);
my_mod #(.mymod_param(2)) u2 (<port_mapping>);
:
endmodule

//------------------------------

module my_mod (...);
parameter mymod_param = 0;
SUB_MOD #(.P1(mymod_param)) sub_inst (<port_mapping>);
endmodule

//------------------------------

module SUB_MOD (...);
parameter P1 = 0;
:
:
endmodule

//------------------------------
AR# 19975
Date Created 09/03/2007
Last Updated 01/07/2009
Status Archive
Type General Article